In recent years, in semiconductor devices such as digital LSIs including a microprocessor, a tendency of decrease in a power supply voltage is developed because of influence of a speeding up of an operation speed and a low power consumption. In such a LSI, its operation power supply voltage tends to be unstable when its impedance changes rapidly. In order to stabilize the power supply voltage and to decrease high frequency noises, a decoupling capacitor is inserted between a power supply voltage line of the LSI and a ground line thereof.
Particularly, since a stable operation in a higher frequency (GHz) range is required in a high speed operation digital LSI, an improvement in performance of the decoupling capacitor such as high frequency followership is desired. Therefore, a capacitor device having a thin film capacitor structure in which a technology capable of reducing a thickness of a dielectric film to increase capacitor capacity is introduced has been devised. Such a thin film capacitor is manufactured based on a thin film process for forming a metallic film, oxide and the like on a base substrate such as silicon. Since a microprocessing is possible in this thin film processes, a capacitor having a low inductance structure can be obtained.
FIGS. 1A to 1E and FIGS. 2A to 2D are section views showing an example of a method of manufacturing a capacitor device having a thin film capacitor according to prior art. In the conventional method of manufacturing a capacitor device, as shown in FIG. 1A and FIG. 1B, after a silicon substrate 100 is prepared, a lower electrode 102 for a capacitor formed of a metallic film is formed on the silicon substrate 100. Thereafter, as shown in FIG. 1C and FIG. 1D, a dielectric film 104a is grown on the lower electrode 102, and then a metallic film 106a for an upper electrode is grown on the dielectric film 104a. 
Next, as shown in FIG. 1E, by etching predetermined portions of the upper electrode metallic film 106a and the dielectric film 104a, an upper electrode 106 for a capacitor and a dielectric film 104 for a capacitor are formed, and a connection portion 102a of the lower electrode 102 are exposed. Thus, a capacitor Q constituted by the lower electrode 102, the capacitor dielectric film 104 and the upper electrode 106 is formed.
Subsequently, as shown in FIG. 2A, a protection insulating film 110 having first and second contact holes 110a and 110b respectively is formed on a connection portion 106x of the upper electrode 106 and the connection portion 102a of the lower electrode 102. This protection insulating film 110 is formed of a polyimide resin film having a thickness of, for example, about 3 μm, and the first and second contact holes 110a and 110b are formed by performing exposure and developing processings for predetermined portions of the polyimide resin film.
Next, as shown in FIG. 2B, a barrier metallic film 112a is formed on the protection insulating film 110 and in the first and second contact holes 110a, 110b. This barrier metallic film 112a is formed of a lamination film, and is formed by being buried in the first and second contact holes 110a and 11b by a sputtering method and electroplating.
Subsequently, as shown in FIG. 2C, the barrier metallic film 112a is patterned by photoetching, whereby an electrode pads 112 are left in the first and second contact holes 110a, 110b. These electrode pads 112 are formed as a metallic plug, which has a thickness of about 3 μm or more, in the first and second contact holes 110a, 110b. 
Next, a resist film (not shown) having an opening portion is formed on the electrode pads 112, and a solder bump is formed in the opening portion by electroless plating, followed by removing the resist film. Thereafter, as shown in FIG. 2D, the solder bump undergoes a thermal treatment (wet back) to reflow, whereby solder bumps 116 are obtained.
In the above described manner, the solder bump 116s are formed in a state where the solder bumps 116 are electrically connected to the connection portion 106x of the upper electrode 106 and the connection portion 102a of the lower electrode 102 through the plug-shaped electrode pads 112 having a thickness of about 3 μm or more.
The above described electrode pads 112 are called an under bump metal (UBM), and have a function to prevent that solder in the solder bumps 116 diffuse into films constituting the capacitor Q disposed under the bumps 116 to react therewith during the foregoing thermal treatment (wet back) process.
As described above, the conventional art adopts the structure in which the first contact holes 110a are formed on the upper electrode 106 of the portion where the lower electrode 102, the dielectric film 104 and the upper electrode 106 are laminated, and in which the upper electrode 106 is electrically connected to the solder bumps 116 through the electrode pads 112 (UBM) formed in the first contact holes 110a. 
Since the above described electrode pads 112a (UBM) need to have a comparatively thick film of thickness of about 3 μm or more to prevent the diffusion of the solder, tensile stress is apt to occur just below the electrode pads 112a due to influences of the electrode pads 112a. Therefore, there is a problem that peeling is prone to occur along an interface between the upper electrode 106a and the dielectric film 104a below the electrode pads 112a. 
Furthermore, since the polyimide resin film having a comparatively high coefficient of thermal expansion (40 to 50 ppm/° C.) is generally used as the protection insulating film 110, tensile stress occurs near the upper electrode 106a below the protection film 110. Therefore, there is a problem that adhesion of the upper electrode 106a and the dielectric film 104a becomes weak and peeling is prone to occur along an interface between them.